LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_SIGNED.ALL
USE IEEE.numeric_std.all
ENTITY test IS
PORT (clock: in std_logic -----clock1加48MHz的信号
row: out std_logic_vector(0 to 7))
END test
ARCHITECTURE behave OF test IS
CONSTANT fp_clka:INTEGER:=12000000 ---扫描信号频率为2Hz
SIGNAL a: INTEGER RANGE 0 TO 12000001
signal saomiao :integer range 0 to 9
SIGNAL clka: std_logic
BEGIN
PROCESS (clock)
BEGIN
IF rising_edge(clock) THEN
IF a<fp_clka then --clka
a<=a+1
clka<=clka
ELSE
a<=0
clka<= NOT clka
end if
end if
end process
process(clka)
BEGIN
IF rising_edge(clka) THEN
saomiao<=saomiao+1
if saomiao=9 then
saomiao<=0
end if
case saomiao is---'1'代表不亮,'0'代盯者枝表亮
when 0 =>row<="01111111"
when 1 =>row<="10111111"
when 2 =>row<="11011111"
when 3 =>row<="11101111"
when 4 =>row<="11110111"
when 5 =>row<="11111011"
when 6 =>row<="11111101"
when 7 =>row<="11111110"
when 8 =>row<="00000000"
when others =>row<="11111111"
END CASE
END IF
end process
END behave
std_logic_vector type does not match integer literal这个错误是说std_logic_vector类型与整形不匹配 主要原因是因为你的q1<= q1+1这句 std_logic_vector不能直接做加法运算。需要先转换成整型饥差，运算之后再转换回来，这需要调用conv_integer 和 conv_std_logic_vector这两个函数。至于其他还有很多语法错误 不多赘述 我在程序中直接给你做了更改 注意if的匹配
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_ARITH.ALL --添加一个库 使橡卜用它里面的函数
USE IEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY cnt315 IS
PORT(clk , clrn : IN STD_LOGIC
q : out std_logic_vector(11 downto 0)) --定义十二位
END cnt315
ARCHITECTURE one OF cnt315 IS
SIGNAL q1 : STD_LOGIC_VECTOR (3 downto 0)
SIGNAL q2 : STD_LOGIC_VECTOR (3 downto 0)
SIGNAL q3 : STD_LOGIC_VECTOR (3 downto 0)
BEGIN
PROCESS(clk,clrn)
--variable cnt : INTEGER RANGE 0 TO 315不知道你设这个变量干嘛
begin
if(clrn = '1') then
q1<= "0000"
q2<= "0000"
q3<= "0000"
elsif(clk'EVENT AND clk = '1') then
if q1= "0100" and q2= "0001" and q3= "0011" then
q1<= "0000"
q2<= "烂如皮0000"
q3<= "0000"
elsif q1="1001" then
q1<= "0000"
if q2 = "1001" then
q2<= "0000"
q3<= conv_logic_vector(conv_integer(q3) + 1,4)--conv_logic_vector(x,y) x是value y是size
else
q2<= conv_logic_vector(conv_integer(q2) + 1,4)
end if
else
q1<= conv_logic_vector(conv_integer(q1) + 1,4)
end if
q <= q3&q2&q1
end if
end process
end one
自动售货机VHDL程序（1）自动售货机VHDL程序如闷察下：
--文件名：pl_auto1.vhd。
--功能散让：货物信息存储，进程控制，硬币处理，余额计算，显示等功能。
--说明：显示的钱数coin的以5角为单位。
library ieee
use ieee.std_logic_arith.all
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity PL_auto1 is
port ( clk:in std_logic --系统时钟
set,get,sel,finish: in std_logic--设定、买、选择、完成信号
coin0,coin1: in std_logic--5角硬币、1元硬币
price,quantity :in std_logic_vector(3 downto 0) --价格、数量数据
item0 , act:out std_logic_vector(3 downto 0) --显示、开关信号
y0,y1 :out std_logic_vector(6 downto 0) --钱数、商品数量显示数据
act10,act5 :out std_logic) --1元硬币、5角硬币
end PL_auto1
architecture behav of PL_auto1 is
type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0)
signal ram :ram_type --定义RAM
signal item: std_logic_vector(1 downto 0)--商品种类
signal coin: std_logic_vector(3 downto 0) --币数计数器
signal pri,qua:std_logic_vector(3 downto 0)--商品单价、数量
signal clk1: std_logic--控制系统的时钟信号
begin
com:process(set,clk1)
variable quan:std_logic_vector(3 downto 0)
begin
if set='1' then ram(conv_integer(item))<=price &quantityact<蚂掘茄="0000"
--把商品的单价、数量置入到RAM
elsif clk1'event and clk1='1' then act5<='0'act10<='0'
if coin0='1' then
if coin<"1001"then coin<=coin+1 --投入5角硬币，coin自加1
else coin<="0000"
end if
elsif coin1='1' then
if coin<"1001"then coin<=coin+2 --投入1元硬币，coin自加2
else coin<="0000"
end if
elsif sel='1' then item<=item+1 --对商品进行循环选择
elsif get='1' then --对商品进行购买
if qua>"0000" and coin>=pri then coin<=coin-priquan:=quan-1
ram(conv_integer(item))<=pri &quan
if item="00" then act<="1000" --购买时，自动售货机对4种商品的 *** 作
elsif item="01" then act<="0100"
elsif item="10" then act<="0010"
elsif item="11" then act<="0001"
end if
end if
elsif finish='1' then--结束交易，退币（找币）
if coin>"0001" then act10<='1'coin<=coin-2--此IF语句完成找币 *** 作
elsif coin>"0000" then act5<='1'coin<=coin-1
else act5<='0'act10<='0'
end if
elsif get='0' then act<="0000"
for i in 4 to 7 loop
pri(i-4)<=ram (conv_integer(item))(i) --商品单价的读取
end loop
for i in 0 to 3 loop
quan(i):=ram(conv_integer(item))(i) --商品数量的读取
end loop
end if
end if
qua<=quan
end process com
m32:process(clk)--此进程完成对32Mhz的脉冲分频
variable q: std_logic_vector( 24 downto 0)
begin
if clk'event and clk='1' then q:=q+1
end if
if q="111111111111111111111111" then clk1<='1'
else clk1<='0'
end if
end process m32
code0:process(item) --商品指示灯译码
begin
case item is
when "00"=>item0<="0111"
when "01"=>item0<="1011"
when "10"=>item0<="1101"
when others=>item0<="1110"
end case
end process
code1: process (coin) --钱数的BCD到七段码的译码
begin
case coin is
when "0000"=>y0<="0000001"
when "0001"=>y0<="1001111"
when "0010"=>y0<="0010010"
when "0011"=>y0<="0000110"
when "0100"=>y0<="1001100"
when "0101"=>y0<="0100100"
when "0110"=>y0<="0100000"
when "0111"=>y0<="0001111"
when "1000"=>y0<="0000000"
when "1001"=>y0<="0000100"
when others=>y0<="1111111"
end case
end process
code2: process (qua) --单价的BCD到七段码的译码
begin
case qua is
when "0000"=>y1<="0000001"
when "0001"=>y1<="1001111"
when "0010"=>y1<="0010010"
when "0011"=>y1<="0000110"
when "0100"=>y1<="1001100"
when "0101"=>y1<="0100100"
when "0110"=>y1<="0100000"
when "0111"=>y1<="0001111"
when "1000"=>y1<="0000000"
when "1001"=>y1<="0000100"
when others=>y1<="1111111"
end case
end process
end behav
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